The present invention is directed to a programmable logic array apparatus, and, in particular, a programmable logic array apparatus which combines techniques of pipelining and simplified addressing with the use of a NAND-type AND plane to achieve reduced power dissipation to the order of about one-tenth the power dissipation of prior art devices while occupying substantially similar area when embodied in an integrated circuit structure.
In modern integrated circuits used in telecommunication applications, voice signals are processed digitally by a micro engine. Such a micro engine is a dedicated signal processor which may employ, for example, an arithmetic logic unit with separate program memory, a data memory, and a coefficient memory. While the data and coefficient memories in such a configuration are generally read-write memories, the program memory is normally implemented as a programmable logic array, or a read-only memory.
The time taken by the micro engine to process one sample is called a "frame", and is, for example, equal to 125 .mu.seconds in pulse code modulation systems operating at an 8 KHz sampling rate. The micro engine is required to perform a certain number of instructions in a given frame, which number of instructions may, for example, range between 256 and 1024. Thus, fast access time is required from instruction storage, often as short as 125 nanosec. Such fast access time dictates a fast programmable logic array or read-only memory structure with attendant high power dissipation, a disadvantage which is desirable to overcome.
Other design criteria of importance in configuring integrated circuits include circuit complexity and area occupied by the integrated circuit. It is desirable to reduce circuit complexity in order that manufacturing may be conducted on a production scale with reliability and repeatability within tight limits. The area occupied by the circuit (the "real estate") is another factor which it is desirable to keep low for economic reasons.
The present invention is designed to provide a low power programmable logic array structure which is economically manufacturable on a production scale and which does not occupy excessive area in an integrated circuit structure.